Ziatech Corporation ZT 89CT04 Dokumentacja

ZT 8832I/O Control ProcessorOPERATING MANUALFor ZT 8832 Revision 0.5and ZT 88CT32 Revision 0.4Reorder Part Number ZT M8832May 10, 19941050 Southwood D

ContentsZT 88CT32 Requirements ... 2-3INSTALLING THE ZT 8832 WITH STD ROM... 2-5Memory Requirement

Processor Description (V40)TA, TB, AND TCALUPSW [FL]Effective AddressGeneratorPS [CS]SS [SS]DS0 [DS]DS1 [ES]PFP [IP]DPQ0-Q3AW [AX]BW[BX]CW [CX]DW [DX]

Processor Description (V40)CPU Functional BlocksThe functional blocks in Figure 5-2 are described below. The NECmnemonic is shown for each block, foll

Processor Description (V40)Strings are addressed differently from other variables. Thesegment register used to point to the source string is DS0 [DS],

Processor Description (V40)For sequentially addressed instructions, the PFP [IP] is incremen-ted by the number of bytes of the current instruction to

Processor Description (V40)General Purpose RegistersAW [AX], BW [BX], CW [CX], and DW [DX]The CPU has four 16-bit general purpose registers. Each of t

Processor Description (V40)Pointers and Index RegistersSP [SP], BP [BP], and IX [SI], IY [DI]The two 16-bit pointer registers are used primarily for s

Processor Description (V40)Loop CounterLCLC is a binary counter used to regulate iterative operations suchas string transfers controlled by the repeat

Processor Description (V40)12 clocks to calculate the effective address using microcode.However, the V40 does all effective address calculations in tw

Processor Description (V40)The control flags are used by the programmer to direct CPUoperation. The control flags are set (logical 1) and reset(logica

Processor Description (V40)number of bits set. This flag is useful for checking the parity ofASCII characters.AC [AF] (Auxiliary Flag) - AC [AF] is se

ContentsObjectives ... 4-18Program Code... 4-19Chapter 5. PR

Processor Description (V40)the array during a string operation. After a string operation iscompleted, the index registers are incremented or decrement

Processor Description (V40)Enhanced ArchitectureThe V40 CPU includes several enhancements that provide an increasein performance over the 8088 micropr

Processor Description (V40)BIU - Bus Interface UnitThe BIU controls the external address, data, and control buses. TheBIU also synchronizes the RESET

Processor Description (V40)the buses at any given time. The bus masters are prioritized in thefollowing order:(1st) DCU - DMA Control Unit(2nd) HLDRQ

Processor Description (V40)WCU - Wait Control UnitThe WCU provides added flexibility for interfacing to memory andI/O that have varying speed requirem

Processor Description (V40)ICU - Interrupt Control UnitInterrupts provide an efficient interface between the V40 CPU andsupporting peripheral devices.

Processor Description (V40)RESETResetting the V40 initializes registers internal to the CPU, VCR,SCU, TCU, ICU, and DCU. The reset states for the CPU

Processor Description (V40)MEMORY AND I/O ADDRESSINGThis section discusses how the V40 communicates with memory andI/O devices. The V40 has a 20-bit a

Processor Description (V40)To the programmer, the V40 address space is organized as acontiguous sequence of up to 1 Mbyte. Data can be addressed in un

Processor Description (V40)The lower 16 of the 20 address lines are also used to address I/Odevices. With 16 bits of address, the V40 can directly acc

ContentsTCKS - Counter/Timer Clock Selection Register ... 6-10RESET... 6-12Chapter

Processor Description (V40)INTERRUPTSThe V40 includes a versatile interrupt structure that supports bothhardware and software initiated interrupts. Ha

Processor Description (V40)Table 5-4Interrupt Sources.Interrupt Source Clocks PrioritySoftware DIVU divide error 45 1DIV divide error 45-55 1CHKIND br

Processor Description (V40)The purpose of an interrupt is to redirect the CPU from its currentactivity to an interrupt service routine designed to han

Processor Description (V40)The vector of an interrupt source must be known before the locationof the service routine address can be determined. The in

Processor Description (V40)Before describing each source of interrupt shown in the vector table, itis useful to summarize the operation of the CPU in

Processor Description (V40)CPU restores the PSW [FL], PS [CS], and PSP [IP]. The single-stepinterrupt is not masked by the IE [IF] bit in the PSW [FL]

Processor Description (V40)Check IndexThe purpose of the check index instruction is to test the index of anarray against an upper and lower limit. The

Processor Description (V40)8080 EMULATIONDesigns based on 8080 and 8085 microprocessors have two majorlimitations: inadequate performance and lack of

Processor Description (V40)A hardware interrupt suspends the 8080 emulation mode. The CPUpushes the PSW [FL] and return address onto the native mode s

Processor Description (V40)Emulation mode uses the BP [BP] register for the stack pointer, ratherthan the native mode SP [SP] register, to reduce the

ContentsInterrupt Nesting ... 8-22Level- or Edge-Triggered... 8-25Finish Int

Chapter 6PROCESSOR CONFIGURATION (V40)Contents PageOVERVIEW ... 6-1VCR - V40 CONFIGURATION REGISTERS

Processor Configuration (V40)VCR - V40 CONFIGURATION REGISTERSThe 12 V40 configuration registers are mapped from I/O addressFFF0h through FFFFh. The r

Processor Configuration (V40)OPCN - On Chip Peripheral Connection RegisterFigure 6-1 shows the OPCN register. Bit 0 must be programmed witha logical 0

Processor Configuration (V40)OPSEL - On Chip Peripheral Selection RegisterThe V40 integrates several of the most common peripheral deviceswith a CPU i

Processor Configuration (V40)OPHA, DULA, IULA, TULA, and SULAFive registers determine the I/O base address of the programmableregisters used to commun

Processor Configuration (V40)The only restriction placed on programming these registers is to besure the peripherals internal to the V40 are not mappe

Processor Configuration (V40)WCY2 - Wait Cycle 2 RegisterThe V40 includes a programmable wait-state generator that interfacesto memory and I/O devices

Processor Configuration (V40)The ZT 8832 does not require any memory wait states if memorydevices with access times less than 250 ns are used. To sele

Processor Configuration (V40)WMB - Wait Memory Boundary RegisterThe ZT 8832 does not require any wait memory wait states if memorydevices with access

Processor Configuration (V40)The Middle Memory Block is defined between the top of the LMBand the bottom of the UMB. Offboard memory (STD bus) require

ContentsPROGRAMMABLE REGISTERS ... 10-5Serial Status Register (SST)... 10-6Serial Command

Processor Configuration (V40)The CS0, CS1, and CS2 (Clock Select 0, 1, and 2) bits select thecounter/timer clock source to be either the reference clo

Processor Configuration (V40)RESETThe V40 configuration registers are automatically initialized to adefault state when power is applied to the V40 and

Chapter 7COUNTER/TIMERS (V40)Contents PageOVERVIEW ... 7-2ZT 8832 SPECIFICS...

Counter/TimersOVERVIEWThis chapter describes the Counter/Timer Control Unit (TCU) andprovides register descriptions.The TCU includes three 16-bit prog

Counter/TimersZT 8832 SPECIFICSThe clock source for each counter/timer is defined in the TCKS V40configuration register. Choices for the clock source

Counter/TimersFUNCTIONAL DESCRIPTIONThe TCU is similar to the 8254 Programmable Interval Timer in thatthe programmable registers are the same. Some re

Counter/TimersMode RegisterThe 8-bit Mode register is programmed to control the operation of thecounter/timers.Clock Select andDivisorThe difference b

Counter/TimersThe Count register and Count Latch are the interface through whichthe count data is transferred between the TCU and the CPU. TheCount re

Counter/TimersPROGRAMMABLE REGISTERSFour separately addressable registers are used for communication withthe TCU. The TMD (Timer Mode) register specif

Counter/TimersTimer Mode Register (TMD)The counter/timers must be initialized with the 8-bit TMD register.The three formats for the TMD register are s

ContentsChapter 12. PARALLEL I/O 12-1OVERVIEW... 12-1ZT 8832 SPECIFICS...

Counter/TimersA new count can be written into the counter/timers at any timewithout reprogramming the TMD register. Care must be taken tobe consistent

Counter/TimersEach counter/timer must be programmed to operate in one of sixpossible count modes. Selection of the count mode is based on theneeds of

Counter/TimersMultiple Latch ModeProgramming the Select Counter bits of the TMD to logical 1sdefines the Multiple Latch command (see Figure 7-4). TheC

Counter/TimersCount RegistersThe Count register is illustrated in Figure 7-5. Unlike the Moderegister, there is one Count register for each of the thr

Counter/TimersThe Multiple Latch command must be used to read the status. Thenumber of required read operations depends on the Read/Write Modeand the

Counter/TimersOPERATIONResetThe TCU registers are not initialized to a default state after power onor reset.Count LatchCommandThe count of any counter

Counter/TimersMultiple Latch CommandThe Multiple Latch command extends the capabilities of the CountLatch command. The Multiple Latch command is used

Counter/TimersModes of OperationThere are six possible count modes for the counter/timers. There arerestrictions for counter/timers 0 and 1 because th

Counter/TimersThe TCTL signal is used to enable and disable the counting operation.The counting operation is enabled if TCTL is high and disabled ifTC

Counter/TimersMode 1 - Retriggerable One-ShotIn Mode 1, counter/timer 2 is triggered to generate a pulse ofprogrammed length. Applications can use thi

ContentsFurther Reference ... 15-7IV.APPENDICESAppendix A. JUMPER CONFIGURATIONS A-1OVERVIEW...

Counter/TimersCLKTCTL2TOUT2COUNT = 0002H(Internal)IOWRCOUNT = 0005H(Internal)IOWRCOUNT = 0003HCount value??0002H 0001H 0000H FFFFH 0002H 0001H 0000H F

Counter/TimersMode 2 - Rate GeneratorThe output of a counter/timer in Mode 2 is high until the programmedcount reaches one, then pulses low for a sing

Counter/TimersCLKTCTL2TOUT2COUNT = 0003H(Internal)IOWRCOUNT = 0006H(Internal)IOWRCOUNT = 0004HCount value??0002H 0001H 0003H 0002H 0002H 0003H 0002H 0

Counter/TimersMode 3 - Square Wave GeneratorThe most common use for Mode 3 is baud rate generation. The V40Serial Control Unit requires that counter/t

Counter/TimersActual counter operation is different for even and odd counts. Foreven counts, the initial count is loaded in one clock pulse anddecreme

Counter/TimersMode 4 - Software Triggered StrobeMode 4 operation provides a means of generating a hardware delaytriggered by software. Counter/timer 2

Counter/TimersCLKTOUT2COUNT = 4(Internal)IOWR(Internal)IOWRCount value??0003H 0002H 0001H 0000H FFFFH FFFEH FFFDH FFFCHTOUT2Count value??0004H 0004H 0

Counter/TimersMode 5 - Hardware Triggered StrobeMode 5 operation provides a means of generating a hardware delaytriggered by a hardware signal. This m

Counter/TimersCLKCOUNT = 0002h(Internal)IOWRTCTL2(Internal)IOWRTOUT2Count value??0004h 0003h 0002h 0001h 0000h FFFFh FFFEh 0003hCOUNT = 0004h COUNT =

Counter/TimersProgrammingThe TCU is enabled and mapped into an I/O address range using theV40 configuration register. The TCU includes three counter/t

ContentsV. INDEXIndex ...i

Chapter 8INTERRUPT CONTROLLER (V40)Contents PageOVERVIEW ... 8-2ZT 8832 SPECIFICS...

Interrupt Controller (V40)OVERVIEWThis chapter describes the Interrupt Control Unit (ICU) and providesregister descriptions.The ICU is a programmable

Interrupt Controller (V40)ZT 8832 SPECIFICSThe inputs to the interrupt controller are connected as shown inTable 8-1.Table 8-1Interrupt Controller Inp

Interrupt Controller (V40)FUNCTIONAL DESCRIPTIONThe format of the ICU programmable registers is the same as theindustry standard 8259 Programmable Int

Interrupt Controller (V40)Interrupt Mask RegisterAll interrupt requests are latched by the Interrupt Request register.The Interrupt Mask register acts

Interrupt Controller (V40)Control LogicThis functional block directs the operation of the other ICU blocksbased on the programmed mode of operation. T

Interrupt Controller (V40)PROGRAMMABLE REGISTERSThe ICU is initialized with Interrupt Initialization Word 1 (IIW1)through Interrupt Initialization Wor

Interrupt Controller (V40)Initialization Words (IIW1, IIW2, IIW3, and IIW4)The ICU must be initialized before it can be used. Initializationconsists o

Interrupt Controller (V40)IIW1 and IIW2Interrupt Initialization Words 1 (IIW1) and 2 (IIW2) are requiredfor ICU initialization. The IIW1 register, sho

Interrupt Controller (V40)The ICU responds to an interrupt acknowledge by supplying theCPU with an interrupt vector based on which interrupt generated

TABLESTable 2–1 STD ROM Jumper Configuration. ... 2-6Table 2–2 DOS MPX Jumper Configuration... 2-8Table 3–1 Devic

Interrupt Controller (V40)IIW4Figure 8-6 shows the architecture for IIW4. IIW1 must be pro-grammed with a logical 1 in the II4 bit if IIW4 is used. A

Interrupt Controller (V40)Operation Words (IMKW, IPFW, and IMDW)Once initialized, the operation of the ICU is controlled with three8-bit values called

Interrupt Controller (V40)IPFWIPFW selects fixed or rotating priorities and the method ofinforming the ICU that an interrupt has been serviced. Operat

Interrupt Controller (V40)The IL0 through IL2 bits designate an interrupt level. This levelis used by certain combinations of the FI, SIL, and RP bits

Interrupt Controller (V40)IMDWIMDW controls the method of reading status from the ICU andenables a special type of interrupt masking.The format of the

Interrupt Controller (V40)The POL bit selects the poll command. The two most commonlyused methods of servicing peripherals in a microprocessor systema

Interrupt Controller (V40)IRQ and IISThe IRQ and IIS status words, shown in Figure 8-10 below, aretaken directly from the Interrupt Request register a

Interrupt Controller (V40)Figure 8-11 shows the IPOL status word. Bits PL0 through PL2define the highest priority interrupt input requesting service.

Interrupt Controller (V40)OPERATIONResetThe ICU registers are not initialized to a default state when power isapplied to the ZT 8832 or after a reset.

Interrupt Controller (V40)The V40 interrupt acknowledge cycle is two machine cycles long andlooks much the same as two I/O read cycles. The difference

TablesTable B–3 J1 Parallel Port Pinout. ... B-11Table B–4 J2 Serial Port (RS-232-C) Pinout... B-12Table B

Interrupt Controller (V40)Interrupt VectorsThe CPU responds to all external interrupt requests by reading an8-bit value from the interrupt device that

Interrupt Controller (V40)Interrupt NestingInterrupt nesting is a powerful structure that allows an interruptcurrently under service to be suspended w

Interrupt Controller (V40)Main ProgramSIIRQ3Interrupt...IRQ3 ServiceRoutineIRQ1InterruptSI...FIRETRETServiceRoutineFIIRQ1Figure 8–13. Nested Interrupt

Interrupt Controller (V40)Next, an IRQ1 request occurs. Since interrupts are automaticallydisabled upon entering a service routine, the IRQ1 request i

Interrupt Controller (V40)Level- or Edge-TriggeredThe two primary methods of sensing interrupt requests are to sensethe logical state (level) or the t

Interrupt Controller (V40)Finish InterruptsThe ICU must be told when a service routine is completed so that thein-service bit of the IIS register can

Interrupt Controller (V40)Automatic Finish InterruptWhen programmed for automatic FI, the ICU automatically executesa nonspecific FI during the interr

Interrupt Controller (V40)Automatic Priority RotationAutomatic priority rotation is used in applications with interruptdevices that are of equal prior

Interrupt Controller (V40)Specific Priority RotationSpecific rotation, like automatic rotation, can be used to change thepriorities of the ICU inputs.

Interrupt Controller (V40)Interrupt MaskingThe ICU inputs are all maskable. The "clear interrupt" instruction canbe executed to disable all

ZIATECH 5+5 WARRANTYFor Ziatech Board- and System-Level Computer ProductsFIVE-YEAR LIMITED WARRANTYProducts manufactured by Ziatech Corporation are co

ILLUSTRATIONSFigure 1–1 Functional Block Diagram. ... 1-5Figure 2–1 STD ROM Jumper Configuration... 2-4Figu

Interrupt Controller (V40)Interrupt StatusThe Interrupt Request (IRQ), Interrupt In-Service (IIS), and InterruptMask (IMKW) registers are available to

Chapter 9DMA CONTROLLER (V40)Contents PageOVERVIEW ... 9-2ZT 8832 SPECIFICS...

DMA Controller (V40)OVERVIEWThis chapter describes the Direct Memory Access Control Unit(DCU) and provides register descriptions.The DCU is a programm

DMA Controller (V40)ZT 8832 SPECIFICSThe ZT 8832 uses one of the four DMA controllers contained in theV40. DMA channel 0 is used to coordinate high sp

DMA Controller (V40)FUNCTIONAL DESCRIPTIONFigure 9-1 illustrates a block diagram of the DCU. The DCU isdivided into six major blocks for explanation p

DMA Controller (V40)Internal Bus InterfaceThe Internal Bus Interface monitors address and data buses forprogramming information. The Internal Bus Inte

DMA Controller (V40)Count RegisterThe Count register includes a 16-bit base count and a 16-bit currentcount. The base count and current count are prog

DMA Controller (V40)PROGRAMMABLE REGISTERSThe DCU occupies 16 consecutive I/O port addresses. Of those 16addresses, 12 are used by the programmer to a

DMA Controller (V40)DMA Initialize Command (DICM)The initialization command, shown in Figure 9-2, includes one bitthat can be set to a logical 1 to re

DMA Controller (V40)For read operations, the BASE bit set to a logical 0 defines whetherthe current register is made available for a read operation or

IllustrationsFigure 7–8 Mode 1 Operation. ... 7-19Figure 7–9 Mode 2 Operation... 7-21Figu

DMA Controller (V40)DMA Base Count/Current Count (DBC/DCC)Two DBC/DCC registers make up the 16-bit DMA count, as shown inFigure 9-4. The two DBC/DCC r

DMA Controller (V40)DMA Base Address/Current Address (DBA/DCA)Three DBA/DCA registers specify the 20-bit address. The format ofthese registers is show

DMA Controller (V40)DMA Device Control (DDC)Two DDC registers select various DCU operating modes. The formatfor these registers is shown in Figure 9-6

DMA Controller (V40)DMA Mode (DMD)Figure 9-7 shows the format of the DMD register. The DMD registercan be accessed with byte or word instructions. The

DMA Controller (V40)Autoinitialize is a feature that automatically reloads the DCU CurrentAddress and Current Count registers from the Base Address an

DMA Controller (V40)DMA Status (DST)The Status register includes information about the currentlyprogrammed state of the DMA channel. The format for DS

DMA Controller (V40)DMA Mask (DMK)The DMK register, shown in Figure 9-9, is used to mask DMArequests made by the DMA channel. The register is accessed

DMA Controller (V40)OPERATIONResetThe DCU registers are initialized after power-on or after a pushbuttonreset. Table 9-2 shows the initialized state.T

DMA Controller (V40)Block Mode TransfersIn block transfer mode, the DCU continues servicing the DMAchannel until the count register is decremented to

Chapter 10SERIAL COMMUNICATIONS (V40)Contents PageOVERVIEW ... 10-2ZT 8832 SPECIFICS...

IllustrationsFigure 11–9 ACC Serial Data Format. ... 11-21Figure 12–1 Parallel Port Functional Diagram... 12-

Serial Communications (V40)OVERVIEWThis chapter describes the Serial Control Unit (SCU) and providesregister descriptions and baud rate information.Th

Serial Communications (V40)FUNCTIONAL DESCRIPTIONThe SCU is similar to the 8251 Serial Control Unit for asynchronousoperation. The SCU does not suppor

Serial Communications (V40)Read/Write ControlThe Read/Write Control block acts as an interface between theinternal registers of the SCU and the CPU. T

Serial Communications (V40)PROGRAMMABLE REGISTERSSix registers are used for communication with the SCU. The SerialTransmit Buffer (STB) and Serial Rec

Serial Communications (V40)Serial Status Register (SST)Figure 10-2 shows the architecture of the SST register, which can beread at any time.Register:S

Serial Communications (V40)Buffer Ready) bit is set to a logical 1 when a character is transferredinto the SRB. Application software uses RBRDY to det

Serial Communications (V40)Serial Command Register (SCM)Figure 10-3 illustrates the SCM register bit map. The SCU is config-ured with the SCM and the

Serial Communications (V40)error conditions occur and remain set until a logical 1 is written to theECL bit.Serial Mode Register(SMD)Figure 10-4 shows

Serial Communications (V40)Enabling even or odd parity is the function of the PS field. Parity isdisabled if a logical 0 is written to bit 4. If parit

Serial Communications (V40)OPERATIONResetThe SCU registers are automatically initialized to a default state whenpower is applied to the ZT 8832, or du

Chapter 1INTRODUCTIONContents PageOVERVIEW ... 1-2Product Definition...

Serial Communications (V40)Serial Data FormatThe SCU supports asynchronous communication. The asynchronousdata format is shown in Figure 10-6 to inclu

Serial Communications (V40)Baud RateThe SCU baud rate is determined by the output of counter/timer 1.Counter/timer 1 must be initialized for a specifi

Serial Communications (V40)The calculation to determine the count value to be programmed intocounter/timer 1 is shown below to be 26. Note that the ca

Serial Communications (V40)If the counter/timers are driven with the external TCLK pin throughconnector J3, instead of with the V40 clock, use the for

Serial Communications (V40)ProgrammingThe SCU is enabled and mapped into an I/O address range using theV40 Configuration register. The SCU includes fo

Chapter 11SERIAL COMMUNICATIONS (82050)Contents PageOVERVIEW ... 11-2ZT 8832 SPECIFICS...

Serial Communications (82050)OVERVIEWThis chapter describes the Asynchronous Communication Controller(ACC) and provides register descriptions and baud

Serial Communications (82050)ZT 8832 SPECIFICSThe ACC serial port, available at connector J2, includes TransmitData (TxD), Receive Data (RxD), and sup

Serial Communications (82050)FUNCTIONAL DESCRIPTIONThe ACC is functionally compatible with the industry standard16450/8250A found in most Personal Com

Serial Communications (82050)Read/Write ControlThe main function of the Read/Write Control block is to supervise theinterface between the ACC internal

IntroductionOVERVIEWThis chapter provides a brief introduction to the ZT 8832. It includesa product definition, a list of product features, a function

Serial Communications (82050)Modem ControlThe Modem Control block includes the serial communicationhandshake, RS-485 buffer control, and parallel port

Serial Communications (82050)PROGRAMMABLE REGISTERSThe remainder of the functional blocks illustrated in Figure 11-1 areprogrammable registers. Table

Serial Communications (82050)Transmit and Receive BufferThe Transmit Buffer, Receive Buffer, and Interrupt Enable registersshare the same addresses as

Serial Communications (82050)Register:Line ControlAddress:03FBhAccess:Read/Write76543210WLSWord Length Select00 5 bits01 6 bits10 7 bits11 8 bitsSTBSt

Serial Communications (82050)The STB bit selects the number of stop bits added to each charactertransmitted and removed from each character received.

Serial Communications (82050)Line StatusThe Line Status register, shown in Figure 11-3, provides informationto the CPU concerning the data transfer. R

Serial Communications (82050)The DR bit indicates the state of the ACC Receive Buffer. A logical 1in the DR bit signals the availability of a characte

Serial Communications (82050)Modem ControlThe Modem Control register, shown in Figure 11-4, includes theserial handshake, RS-485 driver enable, and pa

Serial Communications (82050)The RTS bit (bit 1) defines the state of the Request To Send (RTS)signal. Programming the RTS bit with a logical 0 forces

Serial Communications (82050)Modem StatusFigure 11-5 shows the format of the Modem Status register. All eightbits of this register are used to indicat

IntroductionFeatures of the ZT 8832• STD 32 bus compatible• 8088/8086 code compatible• One 32-pin EPROM socket (480 Kbyte capacity)• Two 32-pin RAM so

Serial Communications (82050)The DCTS, DDSR, and DDCD bits (bits 0, 1, and 3) are set to alogical 1 to indicate that the CTS, DSR, and DCD bits have c

Serial Communications (82050)Divisor LatchThe ACC baud rate is selected by programming the least significantbyte (LSB) and most significant byte (MSB)

Serial Communications (82050)Interrupt IdentifyThe ACC includes 10 sources of interrupts prioritized into fourcategories. The Interrupt Identify regis

Serial Communications (82050)Interrupt EnableThe Interrupt Enable register, shown in Figure 11-8, defines which ofthe four categories of interrupts ar

Serial Communications (82050)OPERATIONResetThe ACC registers are automatically initialized to a default state afterreset. Table 11-3 shows the default

Serial Communications (82050)Serial Data FormatThe ACC supports asynchronous data transfers. The format for theasynchronous data includes start, stop,

Serial Communications (82050)Baud RateThe ACC includes an internal baud rate generator to divide the18.432 MHz reference frequency down to a value equ

Serial Communications (82050)Interrupt and Polled CommunicationSerial data can be transferred and received either by polling status bitsor with interr

Serial Communications (82050)Appendix B includes the pin numbers and signal descriptions of theRS-232-C and RS-485 signals available through connector

Serial Communications (82050)Table 11-5ACC Register Summary.0 DLAB = 0 0 DLAB = 0 1 DLAB = 023Receive Buffer(Read Only)Transmit Buffer(Write Only)Inte

IntroductionDevelopment ConsiderationsZiatech offers two software development systems for ZT 8832applications: STD ROM and DOS MPX.STD ROM (Borland’s

Serial Communications (82050)Table 11-5ACC Register Summary (continued).Register AddressBitNo.0 DLAB = 1 1 DLAB = 146DivisorLatch (LSB)DivisorLatch (M

Chapter 12PARALLEL I/OContents PageOVERVIEW ... 12-1ZT 8832 SPECIFICS...

Parallel I/OZT 8832 SPECIFICSThe three parallel ports are available at connector J1; see page B-11for pin assignments. In addition to the 24 I/O signa

Parallel I/OFUNCTIONAL DESCRIPTIONA functional diagram of each of the 24 I/O signals is illustrated inFigure 12-1. The diagram includes an Output Latc

Parallel I/OOutput BufferThe Output Buffer isolates the Output Latch from connector J1. TheOutput Buffer is disabled and enabled with the 82050 Serial

Parallel I/OPROGRAMMABLE REGISTERSThe 24 parallel I/O signals are accessible through three programmableregisters. The address of each of the registers

Parallel I/OOPERATIONResetThe parallel port outputs are disabled and passively pulled to a TTLhigh after power up or reset.Programming the ParallelPor

Parallel I/OProgramming the Light Emitting Diode• To control the LED, first enable the parallel port byprogramming the OUT2 bit of the 82050 serial po

Chapter 13WATCHDOG TIMERContents PageOVERVIEW ... 13-2ZT 8832 SPECIFICS...

Watchdog TimerOVERVIEWThe primary function of the watchdog timer is to monitor ZT 8832operation and to take corrective action if the ZT 8832 fails to

IntroductionNEC V40Serial PortRS-232 onlyDMAControllerInterruptControllerCounter/TimersNumericData ProcessorSocketWatchdogTimerLocal EPROM1 SocketSeri

Watchdog TimerFUNCTIONAL DESCRIPTIONFigure 13-1 illustrates a functional diagram of the watchdog timer.The diagram includes a timer and a delay for ea

Watchdog TimerStage 1 DelayThe stage 1 delay has a default range of 60 ms minimum and 100 msmaximum. The minimum delay time means that the watchdog ti

Watchdog TimerOPERATIONIn operation, the local CPU is programmed to strobe the watchdogtimer at a periodic rate less than the stage 1 time delay. If t

Watchdog TimerMultiple StagesMany watchdog timers are implemented with a single stage thatgenerates a reset if allowed to time out. The problem with t

Watchdog TimerChanging Time DelaysTable 13-1 shows the two possibilities for the stage delays. Thestage 1 delay is measured from the watchdog strobe t

Watchdog TimerProgrammingThe watchdog timer is armed and strobed with the most significantparallel I/O signal. The watchdog timer is armed with the fo

Chapter 14SBX EXPANSION MODULEContents PageOVERVIEW ... 14-2Features...

SBX Expansion ModuleOVERVIEWThe SBX expansion module provides a method for expanding the I/Ocapabilities of the ZT 8832. The expansion module interfac

SBX Expansion ModuleFeaturesThe major features of the expansion module interface are listed below.• Standard interface for expanding I/O capabilities•

SBX Expansion ModuleZT 8832 SPECIFICSThe expansion module interface is supported through connector J4;the pin assignments given on page B-15. The expa

IntroductionFUNCTIONAL BLOCKSFigure 1-1 illustrates the functional blocks of the ZT 8832. Adescription of each block follows.V40 (µPD70208) ProcessorT

SBX Expansion ModuleINSTALLATIONThe SBX expansion module is installed on the ZT 8832 as shown inFigure 14-1. The module is mechanically secured to the

Chapter 15NUMERIC DATA PROCESSOR (8087)Contents PageOVERVIEW ... 15-2ZT 8832 SPECIFICS...

Numeric Data Processor (8087)OVERVIEWThe V40 is a high performance microprocessor designed for a widevariety of applications. The math capabilities of

Numeric Data Processor (8087)INSTALLATIONThe NDP is installed in an empty socket on the ZT 8832 as shown inFigure 15-1. The 8087-1 (10 MHz) is require

Numeric Data Processor (8087)OPERATIONThe following description is an overview of NDP operation. See thereference section at the end of this chapter f

Numeric Data Processor (8087)Read and Write OperationsIf a read operation is required, the NDP latches the address andoperand as it appears. If the op

Numeric Data Processor (8087)Error Handling and InterruptsA numeric error occurs if an operation is attempted with invalidoperands or if the result of

Numeric Data Processor (8087)Further Reference– Cooner, Jerome, "An Implementation Guide to a ProposedStandard for Floating Point,"Computer,

IV. APPENDICESJUMPER CONFIGURATIONS ... A-1SPECIFICATIONS ... B-1CUSTOMER S

Appendix AJUMPER CONFIGURATIONSContents PageOVERVIEW ... A-1JUMPER OPTIONS...

IntroductionDual Port MemoryThe ZT 8832 is populated with 32 Kbytes of RAM that is accessiblefrom both the local CPU and the STD bus CPU. Arbitration

Jumper ConfigurationsJUMPER OPTIONSTable A-1 below lists the jumpers associated with each option. It alsoindicates the pages on which descriptions of

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions.JUMPER # DESCRIPTIONW1-W6 J2 DCE/DTE Selection - configures the82050 serial port for RS-232

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW7,W8 Battery Backup Device Selection - deter-mines whether

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW16,W17 J2 RS-485 Output Enable - selects themethod of enabl

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW20 Numeric Data Processor Interrupt - enablesthe Numeric Da

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW23-W25 ROM Device Type - configures the ROMsocket for a sel

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW28-W32 STD Bus Dual Port RAM Addressing(20-bit) - defines t

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).W32 W31 W30 W29 W28 Address RangeIn In In In In 00000-07FFFhIn In In In Out 0800

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW33-W36STD Bus Dual Port RAM Addressing(24-bit) - defines th

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW37-W40 STD Bus I/O Port Addressing - defines theaddress ran

SPECIAL EXTENDED WARRANTY OPTIONIn addition to the standard five-year warranty, Ziatech offers, for anominal fee, an extended period of warranty up to

IntroductionSerial CommunicationsThe ZT 8832 includes two asynchronous serial communicationchannels, each with a programmable baud rate generator. The

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW41-W43 Board Select Addressing - defines theboard address i

Jumper ConfigurationsTable A-2ZT 8832 Jumper Descriptions (continued).JUMPER # DESCRIPTIONW44-W46 STD Bus Interrupt Selection - defineswhich STD bus i

Jumper ConfigurationsZT 8832 ICP W1W2W3W4W5W6W28W29W30W31W32W33W34W35W36W37W38W39W40W41W42W43W44W45W46W7 W8W23W15W9W13W14W22W27W26W10W11W12W21W16,W17

Jumper ConfigurationsZT 8832 ICP W1W2W3W4W5W6W28W29W30W31W32W33W34W35W36W37W38W39W40W41W42W43W44W45W46W7 W8W23W15W9W13W14W22W27W26W10W11W12W21W16,W17

Jumper ConfigurationsCUTTABLE TRACESThe ZT 8832 supports several less popular options with cuttabletraces. Cuttable traces are similar in function to

Jumper ConfigurationsTable A-4ZT 8832 Cuttable Traces.TRACE # DESCRIPTIONCT1,CT2 SBX Expansion Module Clock - selects theclock for the SBX expansion m

Jumper ConfigurationsTable A-4ZT 8832 Cuttable Traces (continued).TRACE # DESCRIPTIONCT6 Reserved for Ziatech use.CT7,CT8 Watchdog Timer Time Out - se

Jumper ConfigurationsTable A-4ZT 8832 Cuttable Traces (continued).TRACE # DESCRIPTIONCT9,CT11-CT13SBX Expansion Module Address Expan-sion - increases

Jumper ConfigurationsTable A-4ZT 8832 Cuttable Traces (continued).TRACE # DESCRIPTIONCT10 STD Bus AUX Ground - connects the STDbus AUX GND signal (P1

Jumper ConfigurationsZT 8832 ICP CT1CT2CT5CT3CT4Figure A–3. Cuttable Trace Locations, Component Side.A-21

IntroductionInterrupt ControllerThe ZT 8832 includes an eight-input programmable interruptcontroller with an 8259 architecture. Features of the interr

Jumper ConfigurationsCT11CT12CT13CT9CT8CT7CT6CT10CT14Figure A–4. Cuttable Trace Locations, Solder Side.A-22

Appendix BSPECIFICATIONSContents PageELECTRICAL AND ENVIRONMENTAL ... B-2Absolute Maximum Ratings...

SpecificationsELECTRICAL AND ENVIRONMENTALAbsolute Maximum RatingsSupply Voltage, Vcc ... 0to7VSupply Voltage, AUX

SpecificationsSTD Bus Loading CharacteristicsThe unit load is a convenient method for specifying the input andoutput drive capability of STD bus cards

SpecificationsTable B-1ZT 8832 STD Bus Loading, P Connector.+5 VDCGNDDCPDN*D7/A13 [1]D6/A22 [1]D5/A21 [1]D4/A20 [1]A15A14A13A12A11A10A9A8

SpecificationsTable B-2ZT 8832 STD Bus Loading, E Connector.RSVDXA23XA22XA21XA20RSVD+5 VDCDREQx*GNDD31D30D29D28GNDD15D14D13D12D11D10D9D8MASTER16*AENx*

SpecificationsMECHANICALCard Dimensions & WeightThe ZT 8832 meets the STD 32 bus specification for all mechanicalparameters except for the compone

SpecificationsCOMPONENT SIDE6.5004.5000.4003.610 0.06 RADIUS MAX 2 PL0.15 X 45 CHAM 3 PL0.015 X 45 BEVELBOTH EDGES0.015 X 45CHAMFER 2

Specifications(Component Side)(Solder Side)STD 32 STD 32E13 E14P01 P02E15 E16P03 P04E17 E18P05P06E19 E20P07 P08E21 E22P09 P10E23 E24P11 P12E25 E26P13

SpecificationsZT 8832 ICP J5 J3 J2 J1 J4P1123Figure B–3. Connector Locations.B-9

IntroductionzSBX Expansion Module SocketThe zSBX expansion module socket is provided to customize the I/Ocapabilities of the ZT 8832 to the needs of t

SpecificationsJ1: J1 is a nonlatching 26-pin (dual 13-pin) male transitionconnector with 0.1 inch lead spacing. J1 provides 24 digitalI/O lines, fused

SpecificationsTable B-3J1 Parallel Port Pinout.Pin Signal Port Address[hex]1 MOD24 220h bit 72 MOD11 210h bit 23 MOD23 220h bit 64 MOD10 210h bit 15 M

SpecificationsTable B-4J2 Serial Port (RS-232-C) Pinout.PinDTE DCE Signal Description3 5 TxD Transmit Data5 3 RxD Receive Data7 9 RTS Request To Send9

SpecificationsTable B-5J2 Serial Port (RS-422/485) Pinout.Pin Signal Description1 SDA Send Data (negative)2 SDB Send Data (positive)3 RSA Request To S

SpecificationsTable B-6J3 Counter/Timer and Interrupt Pinout.Pin Signal Description2 TCLK V40 Counter/Timer Clock Input4 TCTL V40 Counter/Timer 2 Cont

SpecificationsTable B-7J4 SBX Expansion Module Pinout.Pin Signal[1]Description1 +12V +12 Volts2 -12V -12 Volts3 GND Signal Ground4 +5V +5 Volts5 RESET

SpecificationsNotes:[1] Signals ending with an asterisk are active low and signals without an asterisk areactive high.[2] The V40 clock is optionally

SpecificationsCablesTB ANSLEY171-25 25 CONDUCTOR28 GA. STRANDED FLAT CABLE 40" 1"PIN 1BLUE WIRETB ANSLEY 622-25S FEMALE25 PIN "D"

SpecificationsTB ANSLEY171-50 50 CONDUCTOR28 GA. STRANDED FLAT CABLE305 2cm (10' 0.75")PIN 1BLUE WIREPIN 1+TB ANSLEY622-503050 PIN FEMAL

SpecificationsTB ANSLEY171-25 25 CONDUCTOR28 GA. STRANDED FLAT CABLE 40" 1"PIN 1BLUE WIRETB ANSLEY 622-25P MALE25 PIN "D" CONNECT

Chapter 2GETTING STARTEDContents PageOVERVIEW ... 2-1UNPACKING...

SpecificationsNOTE 1: OUTSIDE WIRES REMOVED AT THIS POINTNOTE 2: CONNECT THE GROUND BUS BARS TOGETHERNOTE 3: FIRST ARTICLE REQUIRED FOR NEW

SpecificationsFigure B–10. Standard Assembly Diagram.B-21

SpecificationsTIMINGThe ZT 8832 meets the timing requirements outlined in the STD 32bus specification. The SBX expansion module timings are given onth

SpecificationsMA0-MA2t11MCS*MWAIT*IOWRT*MD0-MDFt8t19 t17t12t14t10t7t13t25Symbol Parameter Min Maxt7 Chip select setup to write low 25t8 Chip select ho

SpecificationsMDRQTMDACK*IORD* ORIOWRT*t22t20t21Symbol Parameter Min Maxt20 DMA acknowledge setup to read or write low 25t21 DMA acknowledge hold from

SpecificationsRESETt9 or t18+5 VOLTS4.75VSymbol Parameter Min Maxt9 Power up reset pulse width 50t18 Reset pulse width 50 µsAll times given in nanosec

Appendix CCUSTOMER SUPPORTContents PageOVERVIEW ... C-1REVISION HISTORY...

Customer SupportREVISION HISTORYZT 8832Revision 0The ZT 8832 was originally released on 7/3/89 as Revision 0.Revision 0.1There were no functional chan

Customer SupportSupport was added for 24-bit addressing in either the upper or thelower 8 Mbyte region. See page A-10 for more information.Revision 0.

Customer SupportTECHNICAL ASSISTANCEYou can reach Ziatech’s Customer Support Service at the followingnumber:Corporate Headquarters: (805) 541-0488(805

Getting StartedUNPACKINGPlease check the shipping carton for damage. If the shipping cartonand contents are damaged, notify the carrier and Ziatech fo

Customer SupportRELIABILITYZiatech has taken extra care in the design of the ZT 8832 to ensurereliability. The four major ways in which reliability is

Customer SupportRETURNING FOR SERVICEBefore returning any of Ziatech’s products, you must obtain aReturned Material Authorization (RMA) number by call

Customer SupportZIATECH 5+5 WARRANTYFIVE-YEAR LIMITED WARRANTYProducts manufactured by Ziatech Corporation are covered from the date ofpurchase by a f

Customer SupportSPECIAL EXTENDED WARRANTY OPTIONIn addition to the standard five-year warranty, Ziatech offers, for anominal fee, an extended period o

Appendix DGLOSSARYbackplane The edge of the board that inserts into the STDbus connector. This term is generally used todefine the location of signals

GlossaryCNTRL* Control. This STD bus signal (pin 50) was usedin previous designs for special clock timing onperipheral boards. It may also be used as

Glossaryfrontplane The edge of the board on which the extractor islocated, opposite to the backplane. This term isgenerally used to define the locatio

Glossaryprefetch Instructions are fetched and stored into a queueon the microprocessor prior to execution inorder to optimize performance.push A stack

GlossaryWCU Wait Control Unit. Section of the CPU that candefine a different number of wait states for eachof the three areas of the memory space.D-5

INDEX-A-ACC - Asynchronous Communication Controller ...1-8, 11-1asynchronous data format... 11-21baud rate...

Getting StartedSYSTEM REQUIREMENTSThe ZT 8832 is designed for use with or without an STD busbackplane. For STD bus applications, the ZT 8832 is mechan

Index-B-backplane, definition ...D-1battery backup for local RAM... 1-6jumper

Indexdefinition ... D-1CNTRL* (INTRQ2*), definition... D-2commonly asked

IndexCT10 (STD bus AUX GND) ... A-20CT14 (STD bus dual port RAM addressing)...A-20customer support...

IndexDMA controller (V40) (see DCU - DMA Control Unit) ... 9-1DMD - DMA Mode register...9-13DMK - DMA Mask reg

Index-G-getting started ... 2-1glossary... D-1-I-

IndexInterrupt Enable register (82050 ACC) ... 11-19Interrupt Generation Logic (V40 SCU)... 10-4Interrupt I

Index-L-Light Emitting Diode (LED) ... 12-2programming... 12-7Line Control

IndexModem Control block (82050 ACC) ...11-6Modem Control register (82050 ACC)...11-13Modem Status regi

Indexfrontplane connector J1 ...12-2, B-10functional description... 12-3I/O module mo

IndexV40 SCU ... 10-4reliability... C-5reset...

Getting StartedZT 8832 ICP J5J4 J3 J2 J1STD ROM EPROM32 KBYTE SRAMW28W29W30W31W32W33W34W35W36W37W38W39W40W41W42W43W44W45W46W23W15W9W13W14W22W27W26,W

IndexI/O port addressing... 2-13operation... 10-11programmable r

Indexsystem requirements...2-3-T-TCKS - Timer Clock Selection register ... 6-10TCU - C

IndexBIU - Bus Interface Unit ... 5-19block diagram... 5-6CGU - Clock Ge

IndexW41-W43 (board select addressing) ...A-12W44-W46 (STD bus interrupt selection)... A-13wait-state gen

Getting StartedINSTALLING THE ZT 8832 WITH STD ROMThe fastest way to begin using the ZT 8832 is with the addition ofdevelopment software from Ziatech.

Getting StartedJumper RequirementsTable 2-1 and Figure 2-1 show the correct jumper positioning for theZT 8832 configured to support STD ROM.Table 2-1S

Getting StartedINSTALLING THE ZT 8832 WITH DOS MPXThe DOS Multiprocessing Extension (MPX) software provides adevelopment and operating environment for

CUSTOMER SUPPORTIf you have a technical question, please call Ziatech’sCustomer Support Service at the following number:Corporate Headquarters: (805)

Getting StartedJumper RequirementsTable 2-2 and Figure 2-2 show the correct jumper positioning for theZT 8832 configured to support DOS MPX. This is t

Getting StartedZT 8832 ICP J5J4 J3 J2 J1DOS MPX EPROM32 KBYTE SRAMW28W29W30W31W32W33W34W35W36W37W38W39W40W41W42W43W44W45W46W23W15W9W13W14W22W27W26,W

Getting StartedMEMORYThe ZT 8832 includes memory that is addressable by the local CPUand memory that is dual ported between the local and STD bus CPU.

Getting StartedThe dual port RAM is a 32 Kbyte RAM populated on the ZT 8832. Itis shown on both local and STD bus memory maps because, eventhrough it

Getting StartedI/OThe ZT 8832 includes some I/O devices addressable by the local CPUand other I/O devices addressable by the STD bus CPU. This isshown

Getting StartedFFF0-FFFFh0400-FFEFh03F0-03FFh0380-03EFh0300-037Fh0280-02FFh0240-027Fh0230-023Fh0220-022Fh0210-021Fh0200-020Fh00E0-01FFh00D0-00DFh00B8-

Getting StartedJUMPER OPTIONSThe ZT 8832 includes several jumper options that tailor the operationof the board to the requirements of specific applica

III. USER’S REFERENCETHEORY OF OPERATION ... 3-1APPLICATION EXAMPLES... 4-1PROC

Chapter 3THEORY OF OPERATIONContents PageOVERVIEW ... 3-2COMMONLY ASKED QUESTIONS...

Theory of OperationOVERVIEWThis chapter presents a detailed description of ZT 8832 system leveloperation. Topics discussed include:• Commonly asked qu

PREFACEThis manual describes the operation and use of the ZT 8832 and theZT 88CT32. The boards are functionally identical. However, theZT 88CT32 consu

Theory of OperationCOMMONLY ASKED QUESTIONS1. What software development tools are available?Ziatech supports two software development tools for theZT

Theory of Operation2. Are emulators available for the NEC V40?Yes. Several manufacturers of V40 emulators are listed below.Tektronix, Inc. P.O. Box 48

Theory of Operation3. Can the ZT 8832 access STD bus memory and I/O?The ZT 8832 includes 32 Kbytes of dual port RAM mapped intothe STD bus memory addr

Theory of OperationThe ZT 8832 is a newer generation board that removes many ofthe restrictions found on the ZT 8830. The major differences areoutline

Theory of Operation• More local memory. The ZT 8830 supports a maximumof 32 Kbytes of RAM and 32 Kbytes of EPROM. Withmemory devices currently availab

Theory of OperationDUAL PORT MEMORYThe ZT 8832 is shipped with 32 Kbytes of dual port RAM. Dual portmeans that is it accessible by both the ZT 8832 CP

Theory of OperationSTD BUS AND LOCAL CONTROL PORTSThe STD bus and local control ports increase the control andflexibility of the communication link be

Theory of OperationSTD Bus Control Port ArchitectureFigure 3-1 shows the architecture of the STD bus control port. Bitdefinitions are given on the fol

Theory of Operation• Program the interrupt controller to enable IR5, as discussed inChapter 8;• Remove the hardware mask by programming the LMR bit of

Theory of OperationThe STD Bus Control Port Maskable Interrupt Reset (SMR) bit (bit 3)is programmed by the STD bus CPU to reset an active STD busmaska

PrefaceIII. USER’S REFERENCEChapter 3, "Theory Of Operation," presents a detailed descriptionof ZT 8832 system level operation. Topics discu

Theory of OperationLocal Control Port ArchitectureFigure 3-2 shows the architecture of the local control port. Bitdefinitions are given on the followi

Theory of Operationwrites to the LMI bit are ignored until the interrupt request is clearedby the STD bus CPU writing a logical 1 followed by a logica

Theory of OperationBOARD SELECT OPTIONA ZT 8832 occupies 32 Kbytes of STD bus memory address spaceand 16 bytes of STD bus I/O address space. The memor

Theory of OperationAfter the above steps are completed, install the ZT 8832s into theSTD bus card cage. The ZT 8832s power up not selected. This means

Theory of OperationSTD BUS INTERRUPTSThe ZT 8832 is capable of generating maskable and non-maskableinterrupts to the STD bus CPU. The maskable interru

Theory of OperationThe simplest interrupt architecture is one in which the ZT 8832 doesnot share the interrupt with any other STD bus boards, includin

Theory of OperationThe local interrupt status bit (bit 0) indicates the status of the ZT 8832interrupt request to the STD bus CPU. The STD bus interru

Theory of Operation7. This step applies only to systems with the STD bus CPUconfigured for edge triggered as opposed to level triggeredinterrupts. To

Theory of OperationRESETThe ZT 8832 is reset by any of the following events:• Programming the STD bus control port with a 0Fh, followed bya logical 0,

Theory of Operationpossible for the STD bus CPU to perform these writes as twosequential operations, the SBX expansion module interface requires a15 µ

PrefaceChapter 9, "DMA Controller (V40)," describes the function,configuration, and operation of the V40 Direct Memory AccessControl Unit, a

Theory of OperationTable 3-1 includes a list of devices affected by all sources of reset anda page number for a detailed discussion on the reset state

Chapter 4APPLICATION EXAMPLESContents PageOVERVIEW ... 4-1EXAMPLE 1: V40 INITIALIZATION...

Application ExamplesEXAMPLE 1: V40 INITIALIZATIONObjectivesThe ZT 8832 is designed around the NEC 70208 (V40)microprocessor. This high integration mic

Application ExamplesProgram Code;EXAMPLE #1PROGRAMMING ABSTRACT;; Ziatech Corporation; San Luis Obispo, CA; 06/01/89; THIS PROGRAMMING EXAMPLE ILLUSTR

Application ExamplesTULA EQU 0FFF9H ; TULA I/O ADDRESSTULA_INIT EQU 40H ; TCU OFFSET ADDRESSTCU EQU 256*OPHA_INIT+TULA_INIT; TCU I/O ADDRESS; SERIAL C

Application ExamplesSTACK SEGMENTSTACK SEGMENT STACKDW 20 DUP (?) ; UNINITIALIZED STACKSTACK_TOP LABEL WORD ; TOP OF STACKSTACK ENDS;PROCEDURECODE SEG

Application ExamplesEXAMPLE 2: PERIPHERAL INITIALIZATIONObjectivesThe ZT 8832 contains many of the most commonly used peripheralsfound in STD bus appl

Application Examples; 82050 SERIAL CONTROLLER; V40 SERIAL CONTROLLER AND BAUD RATE TIMER; V40 INTERRUPT CONTROLLER; V40 DMA CONTROLLER;SYSTEM EQUATES;

Application Examples; V40 SCU SERIAL CONTROLLER AND BAUD RATE TIMERTCU_PORT EQU 256*OPHA_INIT+TULA_INIT ; TCU I/O ADDRESSTCU_TMR1 EQU TCU_PORT+1 ; TIM

Application ExamplesMACRO DEFINITIONSPUT MACRO SRCE,DATA ; I/O WRITE MACROMOV DX,SRCEMOV AL,DATAOUT DX,ALENDM;STACK SEGMENTSTACK SEGMENT STACKDW 20 DU

PrefaceChapter 15, "Numeric Data Processor (8087)," explainsinstallation and operation of the optional 8087 Numeric DataProcessor, used to e

Application ExamplesPARALLEL PORT PROCEDURE;; THE ZT 8832 INCLUDES THREE PARALLEL PORTS. THE PARALLEL PORT; OUTPUTS ARE ENABLED AND DISABLED WITH THE

Application ExamplesLED PROCEDURE; THE LED CAN BE TURNED ON AND OFF UNDER SOFTWARE CONTROL. THIS; IS A VALUABLE STATUS INDICATOR, ESPECIALLY DURING TH

Application Examples;; INPUTS: NONE; OUTPUTS: LED IS TURNED OFF; CALLS: NONE; DESTROYS: FLAGSLED_OFF PROC; PRESERVE REGISTER STATUSPUSH AXPUSH DX; TUR

Application ExamplesPUT ACC_MODC,ACC_MODC_INIT; MASK INTERRUPTSPUT ACC_INTC,ACC_INTC_INIT; RESTORE REGISTER CONTENTSPOP DXPOP AXACC_INIT ENDP;V40 SERI

Application ExamplesPUT SCU_CMND,SCU_CMND_INIT; MASK INTERRUPTSPUT SCU_MASK,SCU_MASK_INIT; RESTORE REGISTER STATUSPOP DXPOP AXSCU_INIT ENDP;V40 INTERR

Application ExamplesPUT ICU_MASK,ICU_MASK_INIT; RESTORE THE REGISTER STATUSPOP DXPOP AXICU_INIT ENDP;V40 DMA CONTROLLER PROCEDURE; THE V40 DMA CONTROL

Application Examples;; SINGLE BYTE TRANSFERS; INCREMENT MEMORY ADDRESS; SBX I/O TO RAM OPERATION;; INPUTS: NONE; OUTPUTS: SBX I/O TO RAM MEMORY TRANSF

Application Examples; CALLS: NONE; DESTROYS: FLAGSDCU_READ PROC; PRESERVE REGISTER STATUSPUSH AXPUSH BXPUSH CXPUSH DX; SET UP ADDRESS REGISTERSMOV AX,

Application ExamplesEXAMPLE 3: WATCHDOG TIMERObjectivesA watchdog timer is useful in applications in which a microprocessorcontrols a physical process

Application ExamplesProgram Code;EXAMPLE #3PROGRAMMING ABSTRACT; Ziatech Corporation; San Luis Obispo, CA; 06/01/89; THIS PROGRAMMING EXAMPLE ILLUSTRA

CONTENTSI. INTRODUCTIONChapter 1. INTRODUCTION 1-1OVERVIEW... 1-2Product Definition...

Application ExamplesSTACK SEGMENTSTACK SEGMENT STACKDW 20 DUP (?) ; UNINITIALIZED STACKSTACK_TOP LABEL WORD ; TOP OF STACKSTACK ENDS;DATA SEGMENT; A M

Application ExamplesTYPE_1 DD ? ; SINGLE STEP (NOT USED)TYPE_2 DD ? ; NON-MASKABLE INTERRUPTINT_POINT ENDSPROCEDURESCODE SEGMENT PARAASSUME CS:CODE, S

Application ExamplesAND AL, NOT PAR_PORT_WDOUT DX,ALOR AL,PAR_PORT_WD ; WRITE WATCHDOG BIT HIGHOUT DX,ALPOP DX ; RESTORE REGISTER STATUSPOP AXRET ; EX

Application ExamplesLP3: LOOP LP3CALL WATCHDOG_STB ; STROBE WATCHDOG TIMERJMP LP2 ; REPEATCODE ENDSEND MAIN4-23

Chapter 5PROCESSOR DESCRIPTION (V40)Contents PageOVERVIEW ... 5-2ZT 8832 SPECIFICS...

Processor Description (V40)OVERVIEWThe NEC 70208, commonly known as the V40, is a CMOS micro-processor with a 16-bit internal and 8-bit external data

Processor Description (V40)COMMONLY ASKED QUESTIONS1. Is the V40 pin-compatible with the 80188?The V40 and 80188 are not pin-compatible. This means an

Processor Description (V40)these microprocessors, plus a few more. The added instructionsare outlined below.The following instructions are useful in t

Processor Description (V40)FUNCTIONAL BLOCKSThe V40 can be divided into the major functional blocks listed belowand shown in Figure 5-1 on page 5-6.CP

Processor Description (V40)CPU - Central Processing UnitThe architecture of the CPU functional block is compatible with the8088. The CPU recognizes al